************************************************************************
* auCdl Netlist:
* 
* Library Name:  8bitlowpowerMultiplier
* Top Cell Name: 8bPABAIM_Tree_ZeroDetec
* View Name:     schematic
* Netlisted on:  Nov 25 11:46:05 2012
************************************************************************

*.BIPOLAR
*.RESI = 2000 
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM



************************************************************************
* Library Name: 8bPABAIM
* Cell Name:    AND
* View Name:    schematic
************************************************************************

.SUBCKT AND A B VDD VSS out
*.PININFO A:I B:I VDD:I VSS:I out:B
MM4 out net199 VSS VSS NMOS_VTL W=90n L=50n m=1
MM0 net199 A net183 VSS NMOS_VTL W=90n L=50n m=1
MM3 net183 B VSS VSS NMOS_VTL W=90n L=50n m=1
MM5 out net199 VDD VDD PMOS_VTL W=90n L=50n
MM1 net199 A VDD VDD PMOS_VTL W=90n L=50n m=1
MM2 net199 B VDD VDD PMOS_VTL W=90n L=50n m=1
.ENDS

************************************************************************
* Library Name: 8bitArrayMultiplier
* Cell Name:    HA
* View Name:    schematic
************************************************************************

.SUBCKT HA A B YC YS gnd vdd
*.PININFO A:I B:I gnd:I vdd:I YC:O YS:O
MM2 vdd a_2_74# YC vdd PMOS_VTL W=90n L=50n m=1
MM6 YS a_41_74# vdd vdd PMOS_VTL W=90n L=50n m=1
MM3 a_41_74# a_2_74# vdd vdd PMOS_VTL W=90n L=50n m=1
MM4 a_49_54# B a_41_74# vdd PMOS_VTL W=90n L=50n m=1
MM5 vdd A a_49_54# vdd PMOS_VTL W=90n L=50n m=1
MM1 a_2_74# B vdd vdd PMOS_VTL W=90n L=50n m=1
MM0 vdd A a_2_74# vdd PMOS_VTL W=90n L=50n m=1
MM9 gnd a_2_74# YC gnd NMOS_VTL W=90n L=50n m=1
MM13 YS a_41_74# gnd gnd NMOS_VTL W=90n L=50n m=1
MM10 a_38_6# a_2_74# gnd gnd NMOS_VTL W=90n L=50n m=1
MM11 a_41_74# B a_38_6# gnd NMOS_VTL W=90n L=50n m=1
MM12 a_38_6# A a_41_74# gnd NMOS_VTL W=90n L=50n m=1
MM8 a_2_74# B a_9_6# gnd NMOS_VTL W=90n L=50n m=1
MM7 a_9_6# A gnd gnd NMOS_VTL W=90n L=50n m=1
.ENDS

************************************************************************
* Library Name: 8bPABAIM
* Cell Name:    2bitMultiplier
* View Name:    schematic
************************************************************************

.SUBCKT 2bitMultiplier A<1> A<0> B<1> B<0> GND P<3> P<2> P<1> P<0> VDD
*.PININFO A<1>:I A<0>:I B<1>:I B<0>:I GND:I VDD:I P<3>:O P<2>:O P<1>:O P<0>:O
XI3 A<1> B<1> VDD GND A1B1 / AND
XI2 A<0> B<0> VDD GND P<0> / AND
XI1 A<1> B<0> VDD GND A1B0 / AND
XI0 A<0> B<1> VDD GND A0B1 / AND
XI16 A0B1 A1B0 C0 P<1> GND VDD / HA
XI12 A1B1 C0 P<3> P<2> GND VDD / HA
.ENDS

************************************************************************
* Library Name: 8bitlowpowerMultiplier
* Cell Name:    2-inputORGate
* View Name:    schematic
************************************************************************

.SUBCKT 2-inputORGate A B VDD VSS out
*.PININFO A:I B:I VDD:I VSS:I out:B
MM4 out net036 VSS VSS NMOS_VTL W=90n L=50n m=1
MM3 net036 B VSS VSS NMOS_VTL W=90n L=50n m=1
MM0 net036 A VSS VSS NMOS_VTL W=90n L=50n m=1
MM5 out net036 VDD VDD PMOS_VTL W=90n L=50n m=1
MM2 net38 B VDD VDD PMOS_VTL W=90n L=50n m=1
MM1 net036 A net38 VDD PMOS_VTL W=90n L=50n m=1
.ENDS

************************************************************************
* Library Name: 8bitlowpowerMultiplier
* Cell Name:    FooterNMOS_Row4
* View Name:    schematic
************************************************************************

.SUBCKT FooterNMOS_Row4 GND P<3> P<2> P<1> P<0> P<7> P<6> P<5> P<4> P<11> 
+ P<10> P<9> P<8> P<15> P<14> P<13> P<12> VDD ctrl1 den7 en
*.PININFO GND:I VDD:I den7:I en:I ctrl1:O P<3>:B P<2>:B P<1>:B P<0>:B P<7>:B 
*.PININFO P<6>:B P<5>:B P<4>:B P<11>:B P<10>:B P<9>:B P<8>:B P<15>:B P<14>:B 
*.PININFO P<13>:B P<12>:B
MM14 P<13> ctrl1 GND GND NMOS_VTL W=90n L=50n m=1
MM8 P<9> en GND GND NMOS_VTL W=90n L=50n m=1
MM10 P<1> en GND GND NMOS_VTL W=90n L=50n m=1
MM3 P<5> en GND GND NMOS_VTL W=90n L=50n m=1
MM15 P<12> ctrl1 GND GND NMOS_VTL W=90n L=50n m=1
MM7 P<8> en GND GND NMOS_VTL W=90n L=50n m=1
MM11 P<0> en GND GND NMOS_VTL W=90n L=50n m=1
MM4 P<4> en GND GND NMOS_VTL W=90n L=50n m=1
MM16 P<15> ctrl1 GND GND NMOS_VTL W=90n L=50n m=1
MM6 P<11> en GND GND NMOS_VTL W=90n L=50n m=1
MM5 P<7> en GND GND NMOS_VTL W=90n L=50n m=1
MM1 P<3> en GND GND NMOS_VTL W=90n L=50n m=1
MM13 P<14> ctrl1 GND GND NMOS_VTL W=90n L=50n m=3
MM12 P<10> en GND GND NMOS_VTL W=90n L=50n m=3
MM9 P<2> en GND GND NMOS_VTL W=90n L=50n m=3
MM2 P<6> en GND GND NMOS_VTL W=90n L=50n m=3
XI1 en den7 VDD GND ctrl1 / 2-inputORGate
.ENDS

************************************************************************
* Library Name: 8bitlowpowerMultiplier
* Cell Name:    NOR
* View Name:    schematic
************************************************************************

.SUBCKT NOR A B VDD VSS out
*.PININFO A:I B:I VDD:I VSS:I out:B
MM3 out B VSS VSS NMOS_VTL W=90n L=50n m=1
MM0 out A VSS VSS NMOS_VTL W=90n L=50n m=1
MM2 net20 B VDD VDD PMOS_VTL W=90n L=50n m=1
MM1 out A net20 VDD PMOS_VTL W=90n L=50n m=1
.ENDS

************************************************************************
* Library Name: 8bitlowpowerMultiplier
* Cell Name:    ZeroDetector
* View Name:    schematic
************************************************************************

.SUBCKT ZeroDetector B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0> GND VDD en<4> 
+ en<3> en<2> en<1>
*.PININFO B<7>:I B<6>:I B<5>:I B<4>:I B<3>:I B<2>:I B<1>:I B<0>:I GND:I VDD:I 
*.PININFO en<4>:O en<3>:O en<2>:O en<1>:O
XI3 B<6> B<7> VDD GND en<4> / NOR
XI2 B<4> B<5> VDD GND en<3> / NOR
XI1 B<2> B<3> VDD GND en<2> / NOR
XI0 B<0> B<1> VDD GND en<1> / NOR
.ENDS

************************************************************************
* Library Name: 8bitlowpowerMultiplier
* Cell Name:    FooterNMOS_Row1
* View Name:    schematic
************************************************************************

.SUBCKT FooterNMOS_Row1 GND P<3> P<2> P<1> P<0> P<7> P<6> P<5> P<4> P<11> 
+ P<10> P<9> P<8> P<15> P<14> P<13> P<12> VDD ctrl1 ctrl2 ctrl3 ctrl4 den1 
+ den3 den6 den10 en
*.PININFO GND:I VDD:I den1:I den3:I den6:I den10:I en:I ctrl1:O ctrl2:O 
*.PININFO ctrl3:O ctrl4:O P<3>:B P<2>:B P<1>:B P<0>:B P<7>:B P<6>:B P<5>:B 
*.PININFO P<4>:B P<11>:B P<10>:B P<9>:B P<8>:B P<15>:B P<14>:B P<13>:B P<12>:B
MM14 P<13> ctrl3 GND GND NMOS_VTL W=90n L=50n m=1
MM8 P<9> ctrl2 GND GND NMOS_VTL W=90n L=50n m=1
MM10 P<1> ctrl4 GND GND NMOS_VTL W=90n L=50n m=1
MM3 P<5> ctrl1 GND GND NMOS_VTL W=90n L=50n m=1
MM15 P<12> ctrl3 GND GND NMOS_VTL W=90n L=50n m=1
MM7 P<8> ctrl2 GND GND NMOS_VTL W=90n L=50n m=1
MM11 P<0> ctrl4 GND GND NMOS_VTL W=90n L=50n m=1
MM4 P<4> ctrl1 GND GND NMOS_VTL W=90n L=50n m=1
MM16 P<15> ctrl3 GND GND NMOS_VTL W=90n L=50n m=1
MM6 P<11> ctrl2 GND GND NMOS_VTL W=90n L=50n m=1
MM5 P<7> ctrl1 GND GND NMOS_VTL W=90n L=50n m=1
MM1 P<3> ctrl4 GND GND NMOS_VTL W=90n L=50n m=1
MM13 P<14> ctrl3 GND GND NMOS_VTL W=90n L=50n m=3
MM12 P<10> ctrl2 GND GND NMOS_VTL W=90n L=50n m=3
MM9 P<2> ctrl4 GND GND NMOS_VTL W=90n L=50n m=3
MM2 P<6> ctrl1 GND GND NMOS_VTL W=90n L=50n m=3
XI3 en den10 VDD GND ctrl4 / 2-inputORGate
XI2 en den1 VDD GND ctrl3 / 2-inputORGate
XI1 en den3 VDD GND ctrl2 / 2-inputORGate
XI0 en den6 VDD GND ctrl1 / 2-inputORGate
.ENDS

************************************************************************
* Library Name: 8bitlowpowerMultiplier
* Cell Name:    FooterNMOS_Row2
* View Name:    schematic
************************************************************************

.SUBCKT FooterNMOS_Row2 GND P<3> P<2> P<1> P<0> P<7> P<6> P<5> P<4> P<11> 
+ P<10> P<9> P<8> P<15> P<14> P<13> P<12> VDD ctrl4 ctrl5 ctrl6 den2 den5 den9 
+ en
*.PININFO GND:I VDD:I den2:I den5:I den9:I en:I ctrl4:O ctrl5:O ctrl6:O P<3>:B 
*.PININFO P<2>:B P<1>:B P<0>:B P<7>:B P<6>:B P<5>:B P<4>:B P<11>:B P<10>:B 
*.PININFO P<9>:B P<8>:B P<15>:B P<14>:B P<13>:B P<12>:B
MM14 P<13> ctrl5 GND GND NMOS_VTL W=90n L=50n m=1
MM8 P<9> ctrl4 GND GND NMOS_VTL W=90n L=50n m=1
MM10 P<1> en GND GND NMOS_VTL W=90n L=50n m=1
MM3 P<5> ctrl6 GND GND NMOS_VTL W=90n L=50n m=1
MM15 P<12> ctrl5 GND GND NMOS_VTL W=90n L=50n m=1
MM7 P<8> ctrl4 GND GND NMOS_VTL W=90n L=50n m=1
MM11 P<0> en GND GND NMOS_VTL W=90n L=50n m=1
MM4 P<4> ctrl6 GND GND NMOS_VTL W=90n L=50n m=1
MM16 P<15> ctrl5 GND GND NMOS_VTL W=90n L=50n m=1
MM6 P<11> ctrl4 GND GND NMOS_VTL W=90n L=50n m=1
MM5 P<7> ctrl6 GND GND NMOS_VTL W=90n L=50n m=1
MM1 P<3> en GND GND NMOS_VTL W=90n L=50n m=1
MM13 P<14> ctrl5 GND GND NMOS_VTL W=90n L=50n m=3
MM12 P<10> ctrl4 GND GND NMOS_VTL W=90n L=50n m=3
MM9 P<2> en GND GND NMOS_VTL W=90n L=50n m=3
MM2 P<6> ctrl6 GND GND NMOS_VTL W=90n L=50n m=3
XI3 en den9 VDD GND ctrl6 / 2-inputORGate
XI2 en den2 VDD GND ctrl5 / 2-inputORGate
XI1 en den5 VDD GND ctrl4 / 2-inputORGate
.ENDS

************************************************************************
* Library Name: 8bitlowpowerMultiplier
* Cell Name:    FooterNMOS_Row3
* View Name:    schematic
************************************************************************

.SUBCKT FooterNMOS_Row3 GND P<3> P<2> P<1> P<0> P<7> P<6> P<5> P<4> P<11> 
+ P<10> P<9> P<8> P<15> P<14> P<13> P<12> VDD ctrl5 ctrl6 den4 den8 en
*.PININFO GND:I VDD:I den4:I den8:I en:I ctrl5:O ctrl6:O P<3>:B P<2>:B P<1>:B 
*.PININFO P<0>:B P<7>:B P<6>:B P<5>:B P<4>:B P<11>:B P<10>:B P<9>:B P<8>:B 
*.PININFO P<15>:B P<14>:B P<13>:B P<12>:B
MM14 P<13> ctrl6 GND GND NMOS_VTL W=90n L=50n m=1
MM8 P<9> ctrl5 GND GND NMOS_VTL W=90n L=50n m=1
MM10 P<1> en GND GND NMOS_VTL W=90n L=50n m=1
MM3 P<5> en GND GND NMOS_VTL W=90n L=50n m=1
MM15 P<12> ctrl6 GND GND NMOS_VTL W=90n L=50n m=1
MM7 P<8> ctrl5 GND GND NMOS_VTL W=90n L=50n m=1
MM11 P<0> en GND GND NMOS_VTL W=90n L=50n m=1
MM4 P<4> en GND GND NMOS_VTL W=90n L=50n m=1
MM16 P<15> ctrl6 GND GND NMOS_VTL W=90n L=50n m=1
MM6 P<11> ctrl5 GND GND NMOS_VTL W=90n L=50n m=1
MM5 P<7> en GND GND NMOS_VTL W=90n L=50n m=1
MM1 P<3> en GND GND NMOS_VTL W=90n L=50n m=1
MM13 P<14> ctrl6 GND GND NMOS_VTL W=90n L=50n m=3
MM12 P<10> ctrl5 GND GND NMOS_VTL W=90n L=50n m=3
MM9 P<2> en GND GND NMOS_VTL W=90n L=50n m=3
MM2 P<6> en GND GND NMOS_VTL W=90n L=50n m=3
XI3 en den8 VDD GND ctrl5 / 2-inputORGate
XI2 en den4 VDD GND ctrl6 / 2-inputORGate
.ENDS

************************************************************************
* Library Name: 8bitlowpowerMultiplier
* Cell Name:    BlockMultiplier_ZeroDetector_Control_Tree
* View Name:    schematic
************************************************************************

.SUBCKT BlockMultiplier_ZeroDetector_Control_Tree A<7> A<6> A<5> A<4> A<3> 
+ A<2> A<1> A<0> B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0> GND PP1<2> PP1<1> 
+ PP1<0> PP1<3> PP2<3> PP2<2> PP2<1> PP2<0> PP3<3> PP3<2> PP3<1> PP3<0> PP4<3> 
+ PP4<2> PP4<1> PP4<0> PP5<3> PP5<2> PP5<1> PP5<0> PP6<3> PP6<2> PP6<1> PP6<0> 
+ PP7<3> PP7<2> PP7<1> PP7<0> PP8<3> PP8<2> PP8<1> PP8<0> PP9<3> PP9<2> PP9<1> 
+ PP9<0> PP10<3> PP10<2> PP10<1> PP10<0> PP11<3> PP11<2> PP11<1> PP11<0> 
+ PP12<3> PP12<2> PP12<1> PP12<0> PP13<3> PP13<2> PP13<1> PP13<0> PP14<3> 
+ PP14<2> PP14<1> PP14<0> PP15<3> PP15<2> PP15<1> PP15<0> PP16<1> PP16<0> 
+ PP16<3> PP16<2> VDD den<10> den<9> den<8> den<7> den<6> den<5> den<4> den<3> 
+ den<2> den<1>
*.PININFO A<7>:I A<6>:I A<5>:I A<4>:I A<3>:I A<2>:I A<1>:I A<0>:I B<7>:I 
*.PININFO B<6>:I B<5>:I B<4>:I B<3>:I B<2>:I B<1>:I B<0>:I GND:I VDD:I 
*.PININFO den<10>:I den<9>:I den<8>:I den<7>:I den<6>:I den<5>:I den<4>:I 
*.PININFO den<3>:I den<2>:I den<1>:I PP1<2>:O PP1<1>:O PP1<0>:O PP1<3>:O 
*.PININFO PP2<3>:O PP2<2>:O PP2<1>:O PP2<0>:O PP3<3>:O PP3<2>:O PP3<1>:O 
*.PININFO PP3<0>:O PP4<3>:O PP4<2>:O PP4<1>:O PP4<0>:O PP5<3>:O PP5<2>:O 
*.PININFO PP5<1>:O PP5<0>:O PP6<3>:O PP6<2>:O PP6<1>:O PP6<0>:O PP7<3>:O 
*.PININFO PP7<2>:O PP7<1>:O PP7<0>:O PP8<3>:O PP8<2>:O PP8<1>:O PP8<0>:O 
*.PININFO PP9<3>:O PP9<2>:O PP9<1>:O PP9<0>:O PP10<3>:O PP10<2>:O PP10<1>:O 
*.PININFO PP10<0>:O PP11<3>:O PP11<2>:O PP11<1>:O PP11<0>:O PP12<3>:O 
*.PININFO PP12<2>:O PP12<1>:O PP12<0>:O PP13<3>:O PP13<2>:O PP13<1>:O 
*.PININFO PP13<0>:O PP14<3>:O PP14<2>:O PP14<1>:O PP14<0>:O PP15<3>:O 
*.PININFO PP15<2>:O PP15<1>:O PP15<0>:O PP16<1>:O PP16<0>:O PP16<3>:O PP16<2>:O
XI64 A<1> A<0> B<3> B<2> GND PP15<3> PP15<2> PP15<1> PP15<0> net0129 / 
+ 2bitMultiplier
XI65 A<1> A<0> B<1> B<0> GND PP16<3> PP16<2> PP16<1> PP16<0> net087 / 
+ 2bitMultiplier
XI3 A<1> A<0> B<7> B<6> GND PP10<3> PP10<2> PP10<1> PP10<0> net089 / 
+ 2bitMultiplier
XI15 A<7> A<6> B<7> B<6> GND PP1<3> PP1<2> PP1<1> PP1<0> net0149 / 
+ 2bitMultiplier
XI56 A<5> A<4> B<1> B<0> GND PP11<3> PP11<2> PP11<1> PP11<0> net0102 / 
+ 2bitMultiplier
XI10 A<5> A<4> B<3> B<2> GND PP8<3> PP8<2> PP8<1> PP8<0> net0137 / 
+ 2bitMultiplier
XI62 A<1> A<0> B<5> B<4> GND PP13<3> PP13<2> PP13<1> PP13<0> net52 / 
+ 2bitMultiplier
XI63 A<3> A<2> B<1> B<0> GND PP14<3> PP14<2> PP14<1> PP14<0> net0117 / 
+ 2bitMultiplier
XI5 A<3> A<2> B<5> B<4> GND PP9<3> PP9<2> PP9<1> PP9<0> net057 / 2bitMultiplier
XI9 A<5> A<4> B<5> B<4> GND PP5<3> PP5<2> PP5<1> PP5<0> net0128 / 
+ 2bitMultiplier
XI4 A<3> A<2> B<7> B<6> GND PP6<3> PP6<2> PP6<1> PP6<0> net0149 / 
+ 2bitMultiplier
XI14 A<7> A<6> B<5> B<4> GND PP2<3> PP2<2> PP2<1> PP2<0> net0128 / 
+ 2bitMultiplier
XI13 A<7> A<6> B<3> B<2> GND PP4<3> PP4<2> PP4<1> PP4<0> net0140 / 
+ 2bitMultiplier
XI12 A<7> A<6> B<1> B<0> GND PP7<3> PP7<2> PP7<1> PP7<0> net0147 / 
+ 2bitMultiplier
XI61 A<3> A<2> B<3> B<2> GND PP12<3> PP12<2> PP12<1> PP12<0> net0152 / 
+ 2bitMultiplier
XI8 A<5> A<4> B<7> B<6> GND PP3<3> PP3<2> PP3<1> PP3<0> net0149 / 
+ 2bitMultiplier
MM12 net089 ctrl<7> VDD VDD PMOS_VTL W=90n L=50n m=1
MM11 net057 ctrl<8> VDD VDD PMOS_VTL W=90n L=50n m=1
MM10 net0137 ctrl<9> VDD VDD PMOS_VTL W=90n L=50n m=2
MM9 net52 ctrl<4> VDD VDD PMOS_VTL W=90n L=50n m=1
MM8 net0129 ctrl<2> VDD VDD PMOS_VTL W=90n L=50n m=1
MM7 net0152 ctrl<5> VDD VDD PMOS_VTL W=90n L=50n m=1
MM6 net087 ctrl<1> VDD VDD PMOS_VTL W=90n L=50n m=1
MM5 net0117 ctrl<3> VDD VDD PMOS_VTL W=90n L=50n m=1
MM4 net0102 ctrl<6> VDD VDD PMOS_VTL W=90n L=50n m=1
MM3 net0147 ctrl<10> VDD VDD PMOS_VTL W=90n L=50n m=1
MM2 net0140 en<2> VDD VDD PMOS_VTL W=90n L=50n m=1
MM1 net0128 en<3> VDD VDD PMOS_VTL W=90n L=50n m=2
MM0 net0149 en<4> VDD VDD PMOS_VTL W=90n L=50n m=3
XI19 GND PP1<3> PP1<2> PP1<1> PP1<0> PP3<3> PP3<2> PP3<1> PP3<0> PP6<3> PP6<2> 
+ PP6<1> PP6<0> PP10<3> PP10<2> PP10<1> PP10<0> VDD ctrl<7> den<7> en<4> / 
+ FooterNMOS_Row4
XI11 B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0> GND VDD en<4> en<3> en<2> en<1> / 
+ ZeroDetector
XI16 GND PP7<3> PP7<2> PP7<1> PP7<0> PP11<3> PP11<2> PP11<1> PP11<0> PP14<3> 
+ PP14<2> PP14<1> PP14<0> PP16<3> PP16<2> PP16<1> PP16<0> VDD ctrl<6> ctrl<3> 
+ ctrl<1> ctrl<10> den<1> den<3> den<6> den<10> en<1> / FooterNMOS_Row1
XI17 GND PP4<3> PP4<2> PP4<1> PP4<0> PP8<3> PP8<2> PP8<1> PP8<0> PP12<3> 
+ PP12<2> PP12<1> PP12<0> PP15<3> PP15<2> PP15<1> PP15<0> VDD ctrl<5> ctrl<2> 
+ ctrl<9> den<2> den<5> den<9> en<2> / FooterNMOS_Row2
XI18 GND PP2<3> PP2<2> PP2<1> PP2<0> PP5<3> PP5<2> PP5<1> PP5<0> PP9<3> PP9<2> 
+ PP9<1> PP9<0> PP13<3> PP13<2> PP13<1> PP13<0> VDD ctrl<8> ctrl<4> den<4> 
+ den<8> en<3> / FooterNMOS_Row3
.ENDS

************************************************************************
* Library Name: 8bitArrayMultiplier
* Cell Name:    FA
* View Name:    schematic
************************************************************************

.SUBCKT FA A B C YC YS gnd vdd
*.PININFO A:I B:I C:I gnd:I vdd:I YC:O YS:O
MM22 a_70_6# a_25_6# a_46_6# gnd NMOS_VTL W=90n L=50n m=1
MM20 gnd B a_46_6# gnd NMOS_VTL W=90n L=50n m=1
MM26 YS a_70_6# gnd gnd NMOS_VTL W=90n L=50n m=1
MM14 gnd A a_2_6# gnd NMOS_VTL W=90n L=50n m=1
MM18 gnd A a_33_6# gnd NMOS_VTL W=90n L=50n m=1
MM21 a_46_6# C gnd gnd NMOS_VTL W=90n L=50n m=1
MM23 a_79_6# C a_70_6# gnd NMOS_VTL W=90n L=50n m=1
MM24 a_84_6# B a_79_6# gnd NMOS_VTL W=90n L=50n m=1
MM25 gnd A a_84_6# gnd NMOS_VTL W=90n L=50n m=1
MM27 YC a_25_6# gnd gnd NMOS_VTL W=90n L=50n m=1
MM15 a_2_6# B gnd gnd NMOS_VTL W=90n L=50n m=1
MM19 a_46_6# A gnd gnd NMOS_VTL W=90n L=50n m=1
MM17 a_33_6# B a_25_6# gnd NMOS_VTL W=90n L=50n m=1
MM16 a_25_6# C a_2_6# gnd NMOS_VTL W=90n L=50n m=1
MM7 a_46_54# C vdd vdd PMOS_VTL W=90n L=50n m=1
MM1 a_2_54# B vdd vdd PMOS_VTL W=90n L=50n m=1
MM5 a_46_54# A vdd vdd PMOS_VTL W=90n L=50n m=1
MM0 vdd A a_2_54# vdd PMOS_VTL W=90n L=50n m=1
MM12 YS a_70_6# vdd vdd PMOS_VTL W=90n L=50n m=1
MM8 a_70_6# a_25_6# a_46_54# vdd PMOS_VTL W=90n L=50n m=1
MM10 a_84_46# B a_79_46# vdd PMOS_VTL W=90n L=50n m=1
MM11 vdd A a_84_46# vdd PMOS_VTL W=90n L=50n m=1
MM6 vdd B a_46_54# vdd PMOS_VTL W=90n L=50n m=1
MM13 YC a_25_6# vdd vdd PMOS_VTL W=90n L=50n m=1
MM4 vdd A a_33_54# vdd PMOS_VTL W=90n L=50n m=1
MM3 a_33_54# B a_25_6# vdd PMOS_VTL W=90n L=50n m=1
MM2 a_25_6# C a_2_54# vdd PMOS_VTL W=90n L=50n m=1
MM9 a_79_46# C a_70_6# vdd PMOS_VTL W=90n L=50n m=1
.ENDS

************************************************************************
* Library Name: 8bPABAIM
* Cell Name:    TreeAccumulation
* View Name:    schematic
************************************************************************

.SUBCKT TreeAccumulation P<5> P<4> P<3> P<2> PP1<2> PP1<1> PP1<0> PP2<3> 
+ PP2<2> PP2<1> PP2<0> PP3<3> PP3<2> PP3<1> PP3<0> PP4<3> PP4<2> PP4<1> PP4<0> 
+ PP5<3> PP5<2> PP5<1> PP5<0> PP6<3> PP6<2> PP6<1> PP6<0> PP7<3> PP7<2> PP7<1> 
+ PP7<0> PP8<3> PP8<2> PP8<1> PP8<0> PP9<3> PP9<2> PP9<1> PP9<0> PP10<3> 
+ PP10<2> PP10<1> PP10<0> PP11<3> PP11<2> PP11<1> PP11<0> PP12<3> PP12<2> 
+ PP12<1> PP12<0> PP13<3> PP13<2> PP13<1> PP13<0> PP14<3> PP14<2> PP14<1> 
+ PP14<0> PP15<3> PP15<2> PP15<1> PP15<0> PP16<3> PP16<2> SUM1<14> SUM1<13> 
+ SUM1<12> SUM1<11> SUM1<10> SUM1<9> SUM1<8> SUM1<7> SUM1<6> SUM2<15> SUM2<14> 
+ SUM2<13> SUM2<12> SUM2<11> SUM2<10> SUM2<9> SUM2<8> SUM2<7> SUM2<6> gnd vdd
*.PININFO PP1<2>:I PP1<1>:I PP1<0>:I PP2<3>:I PP2<2>:I PP2<1>:I PP2<0>:I 
*.PININFO PP3<3>:I PP3<2>:I PP3<1>:I PP3<0>:I PP4<3>:I PP4<2>:I PP4<1>:I 
*.PININFO PP4<0>:I PP5<3>:I PP5<2>:I PP5<1>:I PP5<0>:I PP6<3>:I PP6<2>:I 
*.PININFO PP6<1>:I PP6<0>:I PP7<3>:I PP7<2>:I PP7<1>:I PP7<0>:I PP8<3>:I 
*.PININFO PP8<2>:I PP8<1>:I PP8<0>:I PP9<3>:I PP9<2>:I PP9<1>:I PP9<0>:I 
*.PININFO PP10<3>:I PP10<2>:I PP10<1>:I PP10<0>:I PP11<3>:I PP11<2>:I 
*.PININFO PP11<1>:I PP11<0>:I PP12<3>:I PP12<2>:I PP12<1>:I PP12<0>:I 
*.PININFO PP13<3>:I PP13<2>:I PP13<1>:I PP13<0>:I PP14<3>:I PP14<2>:I 
*.PININFO PP14<1>:I PP14<0>:I PP15<3>:I PP15<2>:I PP15<1>:I PP15<0>:I 
*.PININFO PP16<3>:I PP16<2>:I gnd:I vdd:I P<5>:O P<4>:O P<3>:O P<2>:O 
*.PININFO SUM1<14>:O SUM1<13>:O SUM1<12>:O SUM1<11>:O SUM1<10>:O SUM1<9>:O 
*.PININFO SUM1<8>:O SUM1<7>:O SUM1<6>:O SUM2<15>:O SUM2<14>:O SUM2<13>:O 
*.PININFO SUM2<12>:O SUM2<11>:O SUM2<10>:O SUM2<9>:O SUM2<8>:O SUM2<7>:O 
*.PININFO SUM2<6>:O
XI49 PP1<2> C131 C313 SUM2<15> SUM2<14> gnd vdd / FA
XI48 C38 S39 S492 SUM1<10> SUM1<9> gnd vdd / FA
XI47 S310 C39 C492 SUM2<11> SUM2<10> gnd vdd / FA
XI46 S38 C37 C472 SUM2<9> SUM2<8> gnd vdd / FA
XI45 C36 S37 S472 SUM1<8> SUM1<7> gnd vdd / FA
XI42 S491 C481 C482 C39 S39 gnd vdd / FA
XI41 C491 S410 C92 C310 S310 gnd vdd / FA
XI40 C121 C412 S131 C313 S313 gnd vdd / FA
XI39 S411 C410 S112 C311 S311 gnd vdd / FA
XI38 S471 C461 C462 C37 S37 gnd vdd / FA
XI37 C471 S481 S482 C38 S38 gnd vdd / FA
XI36 C45 S461 S462 C36 S36 gnd vdd / FA
XI29 C101 S111 C102 C411 S411 gnd vdd / FA
XI35 S45 C44 S52 C35 S35 gnd vdd / FA
XI27 PP4<0> C71 S81 C481 S481 gnd vdd / FA
XI26 PP4<1> S91 C81 C491 S491 gnd vdd / FA
XI25 S121 C111 C112 C412 S412 gnd vdd / FA
XI24 S101 C91 S102 C410 S410 gnd vdd / FA
XI23 PP7<0> C51 S61 C461 S461 gnd vdd / FA
XI22 PP7<1> S71 C61 C471 S471 gnd vdd / FA
XI21 C41 S51 C42 C45 S45 gnd vdd / FA
XI20 S41 C3 S42 C44 S44 gnd vdd / FA
XI15 PP8<1> PP9<1> PP10<1> C71 S71 gnd vdd / FA
XI14 PP8<0> PP9<0> PP10<0> C61 S61 gnd vdd / FA
XI13 PP11<2> PP12<2> PP13<2> C62 S62 gnd vdd / FA
XI12 PP11<3> PP12<3> PP13<3> C72 S72 gnd vdd / FA
XI11 PP14<1> PP15<1> PP16<3> C3 S3 gnd vdd / FA
XI10 PP14<0> PP15<0> PP16<2> C2 P<2> gnd vdd / FA
XI9 PP11<0> PP12<0> PP13<0> C41 S41 gnd vdd / FA
XI8 PP11<1> PP12<1> PP13<1> C51 S51 gnd vdd / FA
XI7 PP5<1> PP6<1> PP7<3> C91 S91 gnd vdd / FA
XI6 PP5<0> PP6<0> PP7<2> C81 S81 gnd vdd / FA
XI5 PP8<2> PP9<2> PP10<2> C82 S82 gnd vdd / FA
XI4 PP8<3> PP9<3> PP10<3> C92 S92 gnd vdd / FA
XI3 PP2<1> PP3<1> PP4<3> C111 S111 gnd vdd / FA
XI2 PP2<0> PP3<0> PP4<2> C101 S101 gnd vdd / FA
XI1 PP1<0> PP2<2> PP3<2> C121 S121 gnd vdd / FA
XI0 PP1<1> PP2<3> PP3<3> C131 S131 gnd vdd / FA
XI54 S313 C312 SUM1<14> SUM1<13> gnd vdd / HA
XI53 S311 C310 SUM1<12> SUM1<11> gnd vdd / HA
XI52 C311 S312 SUM2<13> SUM2<12> gnd vdd / HA
XI51 C35 S36 SUM2<7> SUM2<6> gnd vdd / HA
XI50 S35 C34 SUM1<6> P<5> gnd vdd / HA
XI44 C43 S44 C34 P<4> gnd vdd / HA
XI43 S412 C411 C312 S312 gnd vdd / HA
XI34 C82 S92 C492 S492 gnd vdd / HA
XI33 C62 S72 C472 S472 gnd vdd / HA
XI32 S82 C72 C482 S482 gnd vdd / HA
XI31 S62 C52 C462 S462 gnd vdd / HA
XI30 S3 C2 C43 P<3> gnd vdd / HA
XI19 PP15<2> PP14<2> C42 S42 gnd vdd / HA
XI18 PP15<3> PP14<3> C52 S52 gnd vdd / HA
XI17 PP6<2> PP5<2> C102 S102 gnd vdd / HA
XI16 PP6<3> PP5<3> C112 S112 gnd vdd / HA
.ENDS

************************************************************************
* Library Name: 8bPABAIM
* Cell Name:    10bitRCA
* View Name:    schematic
************************************************************************

.SUBCKT 10bitRCA CV<15> CV<14> CV<13> CV<12> CV<11> CV<10> CV<9> CV<8> CV<7> 
+ CV<6> P<15> P<14> P<13> P<12> P<11> P<10> P<9> P<8> P<7> P<6> PP1<3> SV<14> 
+ SV<13> SV<12> SV<11> SV<10> SV<9> SV<8> SV<7> SV<6> gnd vdd
*.PININFO CV<15>:I CV<14>:I CV<13>:I CV<12>:I CV<11>:I CV<10>:I CV<9>:I 
*.PININFO CV<8>:I CV<7>:I CV<6>:I PP1<3>:I SV<14>:I SV<13>:I SV<12>:I SV<11>:I 
*.PININFO SV<10>:I SV<9>:I SV<8>:I SV<7>:I SV<6>:I gnd:I vdd:I P<15>:O P<14>:O 
*.PININFO P<13>:O P<12>:O P<11>:O P<10>:O P<9>:O P<8>:O P<7>:O P<6>:O
XI2 CV<6> SV<6> net70 P<6> gnd vdd / HA
XI47 SV<14> CV<14> net21 net18 P<14> gnd vdd / FA
XI46 SV<13> CV<13> net39 net21 P<13> gnd vdd / FA
XI45 SV<12> CV<12> net35 net39 P<12> gnd vdd / FA
XI41 SV<8> CV<8> net42 net46 P<8> gnd vdd / FA
XI42 SV<9> CV<9> net46 net56 P<9> gnd vdd / FA
XI43 SV<10> CV<10> net56 net63 P<10> gnd vdd / FA
XI44 SV<11> CV<11> net63 net35 P<11> gnd vdd / FA
XI40 SV<7> CV<7> net70 net42 P<7> gnd vdd / FA
XI0 PP1<3> CV<15> net18 net056 P<15> gnd vdd / FA
.ENDS

************************************************************************
* Library Name: 8bitlowpowerMultiplier
* Cell Name:    8bPABAIM_Tree_ZeroDetec
* View Name:    schematic
************************************************************************

.SUBCKT 8bPABAIM_Tree_ZeroDetec A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> B<7> 
+ B<6> B<5> B<4> B<3> B<2> B<1> B<0> GND P<15> P<14> P<13> P<12> P<11> P<10> 
+ P<9> P<8> P<7> P<6> P<5> P<4> P<3> P<2> P<1> P<0> VDD den<10> den<9> den<8> 
+ den<7> den<6> den<5> den<4> den<3> den<2> den<1>
*.PININFO A<7>:I A<6>:I A<5>:I A<4>:I A<3>:I A<2>:I A<1>:I A<0>:I B<7>:I 
*.PININFO B<6>:I B<5>:I B<4>:I B<3>:I B<2>:I B<1>:I B<0>:I GND:I VDD:I 
*.PININFO den<10>:I den<9>:I den<8>:I den<7>:I den<6>:I den<5>:I den<4>:I 
*.PININFO den<3>:I den<2>:I den<1>:I P<15>:O P<14>:O P<13>:O P<12>:O P<11>:O 
*.PININFO P<10>:O P<9>:O P<8>:O P<7>:O P<6>:O P<5>:O P<4>:O P<3>:O P<2>:O 
*.PININFO P<1>:O P<0>:O
XI7 A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> B<7> B<6> B<5> B<4> B<3> B<2> B<1> 
+ B<0> GND PP1<2> PP1<1> PP1<0> PP1<3> PP2<3> PP2<2> PP2<1> PP2<0> PP3<3> 
+ PP3<2> PP3<1> PP3<0> PP4<3> PP4<2> PP4<1> PP4<0> PP5<3> PP5<2> PP5<1> PP5<0> 
+ PP6<3> PP6<2> PP6<1> PP6<0> PP7<3> PP7<2> PP7<1> PP7<0> PP8<3> PP8<2> PP8<1> 
+ PP8<0> PP9<3> PP9<2> PP9<1> PP9<0> PP10<3> PP10<2> PP10<1> PP10<0> PP11<3> 
+ PP11<2> PP11<1> PP11<0> PP12<3> PP12<2> PP12<1> PP12<0> PP13<3> PP13<2> 
+ PP13<1> PP13<0> PP14<3> PP14<2> PP14<1> PP14<0> PP15<3> PP15<2> PP15<1> 
+ PP15<0> P<1> P<0> PP16<3> PP16<2> VDD den<10> den<9> den<8> den<7> den<6> 
+ den<5> den<4> den<3> den<2> den<1> / 
+ BlockMultiplier_ZeroDetector_Control_Tree
XI1 P<5> P<4> P<3> P<2> PP1<2> PP1<1> PP1<0> PP2<3> PP2<2> PP2<1> PP2<0> 
+ PP3<3> PP3<2> PP3<1> PP3<0> PP4<3> PP4<2> PP4<1> PP4<0> PP5<3> PP5<2> PP5<1> 
+ PP5<0> PP6<3> PP6<2> PP6<1> PP6<0> PP7<3> PP7<2> PP7<1> PP7<0> PP8<3> PP8<2> 
+ PP8<1> PP8<0> PP9<3> PP9<2> PP9<1> PP9<0> PP10<3> PP10<2> PP10<1> PP10<0> 
+ PP11<3> PP11<2> PP11<1> PP11<0> PP12<3> PP12<2> PP12<1> PP12<0> PP13<3> 
+ PP13<2> PP13<1> PP13<0> PP14<3> PP14<2> PP14<1> PP14<0> PP15<3> PP15<2> 
+ PP15<1> PP15<0> PP16<3> PP16<2> SV<14> SV<13> SV<12> SV<11> SV<10> SV<9> 
+ SV<8> SV<7> SV<6> CV<15> CV<14> CV<13> CV<12> CV<11> CV<10> CV<9> CV<8> 
+ CV<7> CV<6> GND VDD / TreeAccumulation
XI2 CV<15> CV<14> CV<13> CV<12> CV<11> CV<10> CV<9> CV<8> CV<7> CV<6> P<15> 
+ P<14> P<13> P<12> P<11> P<10> P<9> P<8> P<7> P<6> PP1<3> SV<14> SV<13> 
+ SV<12> SV<11> SV<10> SV<9> SV<8> SV<7> SV<6> GND VDD / 10bitRCA
.ENDS
XU111 A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> B<7> 
+ B<6> B<5> B<4> B<3> B<2> B<1> B<0> GND P<15> P<14> P<13> P<12> P<11> P<10> 
+ P<9> P<8> P<7> P<6> P<5> P<4> P<3> P<2> P<1> P<0> VDD den<10> den<9> den<8> 
+ den<7> den<6> den<5> den<4> den<3> den<2> den<1> / 8bPABAIM_Tree_ZeroDetec

